Modern integrated circuits have billions of discrete elements (e.g. transistors). Terminals of the discrete elements are connected by multi-level wiring. The wiring is one of the critical elements of the integrated circuits determining an upper limit of clock frequencies of the integrated circuits. The wiring has to be designed in a way that it enables error free propagation of electrical signals synchronized with the clock frequency. This means that electrical signals have to be received at receiving terminals within a time window in a tact interval. The receipt of electrical signals has to be error free. As usual, it requires not only timely receiving of the electrical signals at the receiving terminals, but also satisfying a required slew rate of the electrical signals at the receiving terminals and/or minimization of cross talk between the wires (i.e., minimization of common run length).
Modern digital circuitry has tolerances for error free propagation of electrical signals in the picosecond range. The problem of finding an appropriate wiring topology is complicated by the need to design interconnect lines and the cells generating signals in the interconnect lines complying with the design rules. The last, but not least, problem is that for every next generation of integrated circuits (IC) on the technology development roadmap of semiconductors, the topological requirements for the layout of wiring get further restrained.